Design and Verification of SDRAM Controller Based on FPGA

Authors: Song Won Kil, Dong Ho Kim, Hyo Il Ri

SDRAM (Synchronous DRAM) has become the memory standard in many digital system designs, because of low price and high read/write speed. In this paper, Based on the analysis of the working principle and characteristics of SDRAM, an SDRAM controller design method is proposed based on field programmable logic gate array FPGA. In order to reduce resource consumption and increase the read and write speed of SDRAM, the performance control of SDRAM is further optimized. We designed SDRAM controller by using Verilog HDL and Altera Quartus II 14.1 software, and simulated about this design with Model Sim-Altera 10.3c software. Then we verified this design by using Cyclone V 5CSEMA5F31C6 FPGA in DE1-SoC development board. The verification results show that the SDRAM is initialized successfully, the input and output data are completely consistent, and it has stable refresh and read and write functions. The SDRAM controller design meets the requirements.


Journal: Journal of Computer and Communications
DOI: 10.4236/jcc.2020.87002(PDF)
Paper Id: 101322 (metadata)

See also: Comments to Paper

About scirp

(SCIRP: is an academic publisher of open access journals. It also publishes academic books and conference proceedings. SCIRP currently has more than 200 open access journals in the areas of science, technology and medicine. Readers can download papers for free and enjoy reuse rights based on a Creative Commons license. Authors hold copyright with no restrictions. SCIRP calculates different metrics on article and journal level. Citations of published papers are shown based on Google Scholar and CrossRef. Most of our journals have been indexed by several world class databases. All papers are archived by PORTICO to guarantee their availability for centuries to come.
This entry was posted in JCC. Bookmark the permalink.

Leave a Reply

Your email address will not be published. Required fields are marked *